Course Catalog & Credential Pathway — Dwg. No. PF-002F
A field branch of the Construction Track, for students aimed at silicon itself — reinforcement learning applied to a floorplan instead of a game board.
Field branch of Dwg. No. PF-002, The Construction Track — same core sequence through Phase II, concentrated here into digital logic and physical layout from Phase II onward. See also Dwg. No. PF-001, The Verification Track.
Five core strands, plus the domain strand this branch concentrates in
No floorplans yet, and no logic gates yet either. Two years of straight math and programming fundamentals, identical to the core Construction Track.
Precalculus, Accelerated
Compressed to clear room for calculus by grade 11 — the standard on-ramp for anyone headed toward a quantitative degree.
Programming I — Python
Variables, control flow, functions, data structures. Fluency, not tricks.
Discrete Mathematics & Logic
Sets, proofs, graphs, combinatorics — the math CS theory actually runs on, usually skipped until it's overdue.
Technical Writing for Research
Writing a clear methods section and an honest results section — the two paragraphs every paper lives or dies on.
The math and CS sequences converge into an actual first model, same as the core track. The hardware layer begins concurrently — by the end of Phase II a student can both train a small model and hand-route a digital circuit's timing closure.
Calculus I & II
Through multivariable and the gradient — backpropagation is the chain rule with bookkeeping, and it should read that way.
MATH 101
Linear Algebra
Vector spaces, eigendecomposition, matrix calculus. Every tensor operation is this course wearing a framework's syntax.
MATH 101
Probability & Statistics for ML
Distributions, estimation, Bayes — framed toward loss functions and uncertainty, not toward the social-science stats track.
Data Structures & Algorithms
Complexity analysis and the standard structures, drilled to fluency — still the baseline technical-interview bar at every AI lab.
CS 100
Intro to Machine Learning
Regression through a first neural net, built from array operations before any framework is allowed to hide the mechanics.
MATH 210, STAT 220
Research Seminar — Reading Group
Weekly seminal-paper reads (perceptron through transformers), presented and defended aloud, not just summarized.
Digital Logic & Computer Architecture
Combinational and sequential logic, pipelining, and the microarchitecture vocabulary underneath every chip a design tool is asked to lay out.
CS 210
VLSI Design & Physical Layout
Floorplanning, placement, routing, and timing closure done by hand first — the ground truth a graduate needs before trusting an autonomous design tool's output.
ENG 225
Here the domain degree takes over from the general CS/applied-math track. A computer engineering or electrical engineering-plus-CS program replaces DEG 300 — chip design employers hire for silicon fluency first.
Computer / Electrical Engineering Degree
Formal core in a computer engineering or electrical engineering-plus-CS program — silicon fluency is what chip design employers hire for first.
Reinforcement Learning for Chip Floorplanning
RL-based placement and routing in the AlphaChip tradition, plus the commercial autonomous-design tooling now shipping from major EDA vendors.
EDA 235, ML 230
Deep Reinforcement Learning
Policy gradients, value functions, and the RL methods behind systems like AlphaChip, taught directly against a floorplanning or routing benchmark rather than as a generic survey.
ML 230
Systems for ML
Distributed training, GPU/accelerator programming, and the infrastructure a large-scale floorplanning search needs to explore a design space at any real breadth.
CS 210
Supervised Research Practicum
Placement inside a semiconductor or EDA-tooling group, with a mentor of record. Graded on a reproduction that actually reproduces, or a contribution that gets merged.
RES 240, ML 310
Capstone — Build & Ship
One model or tool — an RL-based placer, a floorplanning benchmark — taken from idea to a deployed, load-bearing artifact against a real layout problem.
ENG 320, RES 350
No end date: the ML baseline moves every conference cycle, and the fabrication-process baseline — node shrinks, new tool releases from Cadence, Synopsys, and NVIDIA — moves on its own industry schedule that a purely computational graduate can lose track of.